Throughput performance of ARQ schemes on a markov bit‐error channel
Masaharu Komatsu, Katsuaki Okamoto, Kozo Kinoshita · Electronics and Communications in Japan (Part I Communications) · 1995
Abstract The performances of ARQ schemes depend on the error process. This paper evaluates the throughput performances of Stop‐and‐wait ARQ and Go‐back‐N ARQ schemes on an unslotted channel or a slotted channel. In these channels, channel time is divided into fixed size intervals called bit‐time and channel state changes according to a two‐state Markov chain. the two‐state Markov chain has two states, S1 and S2. In state S1, a bit‐error never occurs; while in state S2 a bit‐error occurs with probability one. Also, the property of the process is uniquely determined by two transition probabilities, i.e., the transition probability p1 from S1 to S2 and the transition probability p2 from S2 to S1. From the analysis, it is found that the state changes less frequently for larger decay factor δ( =1 ‐ p1 ‐ p2) and the throughput performances of the ARQs depend strongly on the decay factor for fixed bit‐error rates. Furthermore, the numerical examples show that for a given bit‐error, round‐trip delay, packet length, and overhead length, their throughput and optimum packet length giving the maximum throughput become larger when the decay factor becomes larger.