Symbolic functional vector generation for VHDL specifications
Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto · 1999
Veri cation of the functional correctness of VHDL speci cations is one of the primary and most time consuming task of design.However, it must necessarily be an incomplete task since it is impossible to completely exercise the speci cation by exhaustively applying all input patterns.The paper aims at presenting a two-step strategy based o n symbolic analysis of the VHDL speci cation, using a behavioral fault model.First, we generate a reduced number of functional test vectors for each process of the speci cation which allow complete code statement coverage and bit coverage, allowing the identi cation of possible redundancies in the VHDL process.Then, through the de nition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when it is interconnected to other processes.If this is not the case, the analysis of the non-applicable inputs provides identi cation of possible code redundancies and design errors.Experimental results show that bit coverage provides complete statement coverage and a more detailed identi cation of possible design errors.