A realistic fault model and test algorithms for static random access memories
R. Dekker, F. P. M. Beenker, L. Thijssen · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990
Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses.>