A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip
Hsiu-Cheng Chang, Jiawei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun‐Hao Chang, Zemin Chen, Wei-Sen Yang, Chien‐Chang Lin, Ching‐Wen Chen, Jinn-Shan Wang, Jiun-In Guo · 2007
A dynamic quality-scalable H.264 video encoder is presented for power-adaptive video encoding. In 0.13mum CMOS technology, it requires 470kgates/13.3kB SRAM and consumes 7mW/183mW in encoding 30fps CIF/HD720 video. Compared to the state-of-the-art design for real-time HD720 video encoding, a 49% reduction in gate count and a 61% reduction in internal memory is achieved