Design and implementation of modified iterative logarithmic multiplier for low-power and area-efficient applications
Iosr Journals, Rohan Appasaheb Borgalli, Hari Pratap Gautam, Winner George Parayil · Figshare · 2014
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, less area, more accuracy or even combination of them in multiplier. This paper presents a simple and efficient logarithmic multiplier with the possibility to achieve a maximum accuracy with less area and low power Consumption through an iterative procedure with recursive