Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Nathan N. Sadler, Daniel J. Sorin · Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design · 2006
We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and area. The two approaches are: (1) parity on the L1D with write-through to an ECC-protected L2, and (2) ECC protection on the L1D. Qualitatively, the first approach requires a write-through LID, which places a large bandwidth and power demand on the L2. The second approach adds more bits in the LID for error protection, which adds to the L1D's area and power while degrading its performance. Our quantitative results show that the relative costs of the second approach are small and that its benefits outweigh these costs. We also present a new error protection scheme, called the punctured ECC recovery cache (PERC), that achieves the best features of both existing schemes.