A new RISC processor architecture for MPEG-2 decoding
Keita Yamada, M. Kojima, Toshihisa Shimizu, Fumiaki Sato, Tadanori Mizuno · IEEE Transactions on Consumer Electronics · 2002
Most of the processors for MPEG-2 decoding adopt a four-way or more complex architecture to decrease the calculation cycles, but on the other hand the processors for system control a need more simple architecture. The architecture of an system on a chip (SOC) processor must satisfy both requirements, therefore a two-way RISC processor architecture using a four-multiply-add operation is proposed. Next, a simple IDCT algorithm to decrease the calculation cycles using the four-multiply-add operation is investigated. Also, the data transfer for IDCT is discussed and it is found to be possible to carry out the transfer process in parallel with the calculation. As a result of the evaluation for the total calculation cycle, it is concluded that the two-way RISC processor with a 250 MHz clock can be applied to a SOC for MPEG-2 decoding. In other words, it is suitable for SOCs for DTV and DVD.