Modelling and synthesis of automata in HDLs
Sławomir Chmielewski, Marek Węgrzyn · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2006
In the paper digital modelling and synthesis of automata in Hardware Description Languages is described. There is presented different kinds of automata and methods of realization using languages like VHDL and Verilog. Basic models for control units are: Finite State Machine (FSM), Algorithmic State Machine (ASM) and Linked State Machine (LSM). FSM, ASM and LSM can be represented graphically, which would help a designer to visualize and design in a more efficient way. On the other hand, a designer needs a fast and direct way to convert the considered designs into Hardware Description Language (HDL) codes for simulation and analysis it for synthesis and implementation.