Load balancing in a switch without buffers
Saad Mneimneh · 2006
A load balanced switch consists of k output queued switches, each running at a speedup (the ratio of internal memory speed to external line speed) of N/k, where N is the number of input and output ports. With such an architecture, and for some classes of traffic patterns, simply spreading the traffic among the k switches achieves 100% throughput (thus the term load balancing). However, reordering among packets of the same flow may occur, which becomes a major concern. Input and output buffers have been used in the literature to avoid this problem. This paper proves two main results: (1) it is impossible to achieve 100% throughput and no reordering for a load balanced switch without buffers, and (2) it is possible to achieve 100% throughput and limited reordering for a load balanced switch without buffers. The latter result implies that it is possible to achieve 100% throughput and no reordering for a load balanced switch with output buffers only