Test scheduling with power–time tradeoff and hot-spot avoidance using MILP
Mehrdad Nourani, J. Chin · IEE Proceedings - Computers and Digital Techniques · 2004
A test scheduling methodology for core-based systems on a chip allows tradeoffs between system power dissipation and overall test time while avoiding the formation of hot-spots. The basic strategy is to use a power profile of nonembedded cores over time and grids to find the best mix of their test pattern subsets that satisfy power and/or time constraints. Two mixed-integer linear programming formulations are presented to globally perform power–time tradeoff and produce the SoC test schedule. Many constraints including peak/average power dissipation of cores, physical/structural power distribution of cores, time/sequencing requirements, and ATE-pin limitation are also incorporated within the formulation.