A note on 'free accumulation' in VLSI filter architectures
Peter R. Cappello, Ken Steiglitz · IEEE Transactions on Circuits and Systems · 1985
Completely pipelined inner product architectures are presented for FIR filtering and linear transformation. The designs use only full adders, organized to form multipliers. By cascading these multiplier structures, no additional area or time is needed to sum their products. The merits of the FFT are briefly reconsidered in the context of high throughput VLSI structures for digital signal processing.