Design of an IPv4/IPv6 Translator Based on SOPC Technology
Waixi Liu, Run-hua Tang, Hui Li, Xiao Hui Hu · 2008
As the key device of IPv4-IPv6 interconnection, an IPv4/IPv6 translator has to support high forward speed. However, there is no existing solution published to satisfy the requirement. In this paper, a solution of IPv4/IPv6 translator based on SOPC (system on programmable chip) technology is proposed. It is based on top-down design methodology. In the development process, VHDL programming and schematic design are both used and the system is implemented on one FPGA chip. Test results show that its maximum forward speed is 800 Mbps and its delay time is 40 ns from v4 to v6 network, and 96 ns from IPv6 to IPv4.