A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems
Youchang Kim, Gyeonghoon Kim, Injoon Hong, Dong‐Hyun Kim, Hoi‐Jun Yoo · 2014
A neural network task scheduler (NNTS) is proposed for the congestion-minimized network-on-chip in multi-core systems. The NNTS is composed of a near-optimal task assignment (NOTA) algorithm and a reconfigurable precision neural network accelerator (RP-NNA). The NOTA adopting a neural network is proposed to predict and avoid the network congestion intelligently. And the RP-NNA is implemented to improve the throughput of NOTA with dynamically adjustable precision. In the case that the NNTS is integrated into a NoC-based multi-core SoC for the augmented reality applications, 79.2% prediction accuracy of NoC communication pattern is achieved and the overall latency is reduced by 24.4%. As a result, the RP-NNA consumes only 4.9 mW and improves the energy efficiency of system by 22.7%.