Multiplier/shifter design tradeoffs in a 32-bit microprocessor
Veljko M. Milutinović, M. Bettinger, Wolfgang Helbig · IEEE Transactions on Computers · 1989
The authors concentrate on design tradeoffs between the bit-serial multiplier and the full barrel shifter combined with a large register file. They analyze and compare three alternatives for a given set of technology related parameters and a given set of higher level language (HLL) benchmarks. Although their basic concern is the design of a 32-bit GaAs microprocessor on a single chip, the implications of the results are more general.>