On fault simulation for synchronous sequential circuits
Irith Pomeranz, Sudhakar M. Reddy · IEEE Transactions on Computers · 1995
We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.>