COMPILER TECHNIQUES FOR OPTIMIZING MEMORY AND REGISTER USAGE ON THE CRAY 2
C. Eisenbeis, William Jalby, A. Lichnewsky · International Journal of High Speed Computing · 1990
In a previous work [3], a cyclic scheduling method was shown efficient to generate vector code for the Cray-2 architecture, and compared to existing compilers. This method was using the framework of microcode compaction through a simplified model of the Cray-2 vector instruction stream. In this paper, we further elaborate on two issues: how to model the machine architecture within the underlying cyclic scheduling method, and the performance of the register allocation technique that must endeavour to make a good use of the scarce resource represented by vector registers. Comparisons with other related work in the area of RISC and VLIW processors are presented as well as performance data.