Evolutionary graph generation system with symbolicverification for arithmetic circuit design
Naofumi Homma, Takafumi Aoki, Takahiro Higuchi · Electronics Letters · 2000
A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within ~2.2 h.