A single-chip U-interface transceiver for ISDN
D. Sallaerts, Dirk Rabaey, R. Dierckx, Jan Sevenhans, Didier Haspeslagh, B. De Ceulaer · IEEE Journal of Solid-State Circuits · 1987
The authors discuss system and implementation aspects of a 144 kbit/s one-chip U-transceiver based on echo-cancellation techniques using the MMS43 line code and a Barker synchronization word for bit and frame timing, and including a 1-kb/s transparent channel for maintenance purposes. The LSI is realized by a 2-/spl mu/m CMOS, double-metal, double-poly technology shrinkable to a 1.5-/spl mu/m technology and packaged in a 28-pin DIL (dual in-line) package.