Implementation of the IPv6 datagram processing on the FPGA chips
Rade R. Bozovic, Aleksandra Simljanic, Zoran Čiča · 2013
This work presents the VHDL design of the IPv6 datagram processing module. The aim of the module is to process IPv6 datagram header, then to forward relevant data from the header to output ports, as well as to forward the complete IPv6 header to the output ports. Design of the module and simulation for its verification of its performance was done in Active HDL, while synthesys was done in the Xilinx software.