Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator
Leonid Yavits, Amir Morad, Ran Ginosar · IEEE Transactions on Computers · 2014
This study presents a computer architecture, where a last-level cache and a SIMD accelerator are replaced by an associative processor. Associative processor combines data storage and data processing, and functions as a massively parallel SIMD processor and a memory at the same time. An analytic performance model of this computer architecture is introduced. Comparative analysis supported by cycle-accurate simulation and emulation shows that this architecture may outperform a conventional computer architecture comprising a SIMD coprocessor and a shared last-level cache while consuming less power.