An asynchronous array architecture for 16 × 1 DCT-4/DST-4 on a 65nm Achronix SPD60 FPGA
Arjuna Madanayake, Dale H. Mugler, Nilanka Rajapaksha · 2011
Asynchronous (clock-free) digital VLSI is emerging for DSP that requires both high-throughput and low power consumption. Achronix FPGA technology is based on asynchronous quasi delay insensitive logic and offers maximum speeds of upto 1.5 GHz at the 65nm node, with lower-power devices based on INTEL 22nm CMOS technology expected in late 2011. Here, we explore the realization of DCT-4 and DST-4 algorithms, which are extremely important building blocks for modern multimedia, video and image processing systems. We employ 16×1 transforms using Astola's Algorithm, chosen for its uniform delay spread, modularity, and regularity, making this algorithm is well-suited for asynchronous FPGAs. Design examples ranging from 4-12 bit data word sizes are provided with experimental details, including speeds of operation in the range 523.3-337.1 MHz, respectively.