Addressing programmability of Accelerator-based Seismic Applications
J. -M. Cela · 72nd EAGE Conference and Exhibition - Workshops and Fieldtrips · 2010
Lately, hardware accelerators have demonstrated their capability to propel algorithms like RTM into real production codes in O&G industry. Currently, symmetric multi-core technology is not able to achieve the accelerators performance. For instance, the soon to be released family of multi-core chips with up to 48 cores will achieve peak performance which account just for the base-line performance of the accelerators, chip-wise. Up to last year, the accelerator race was a three-horse deal, the main accelerators contenders were: IBM Cell/B.E., GPUs and FPGAs. However, the IBM announcement regarding the Cell/B.E. processors demise leaves only two accelerators standing. Therefore, in this talk we will address a comparative of the RTM execution using Nvidia GPUs and Convey FPGA-based solution. Moreover, the accelerators programmability is a key point. We will introduce the in-house GMAC programming model for GPUs. GMAC helps to hide the (host-device) memory management and communications to the user, thus allowing the development of simplify but efficient programs. Also, we present real RTM execution results that demonstrate the viability of this approach. The next figure shows a comparative between GMAC and a native CUDA code, solving the same stencil problems, as can be seen the performance is competitive but the GMAC user code is simpler (2 domains single host example).