Multi-user memory management micro style
J. Willott · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1982
The author describes a memory management system that permits the 16-bit 8600 computer to take full advantage of a sophisticated multi-user operating system like Xenix. A 2-level memory addressing scheme makes it possible for the CPU to allot memory from a pool of 4k-byte pages. The CPU can thus meet memory requirements by assembling free pages that are not necessarily contiguous, so that user demands can be dynamically adjusted. A system of software switches flexibly controls read and write access, while error detection and correction circuitry provides a high degree of confidence in system performance.