Fast Protocol Decoding in Parallel with FPGA Hardware
Han Li, Yuzhuo Fu, Ting Liu, Jiafang Wang · 2014
Current studies about decoding Fast protocol in the FPGA platform are always implemented using serial communication technique and for some certain Fast Templates. This paper presents the FPGA hardware design of accelerating the decoding process in parallel and cutting down the cost of changing Fast Templates with flexible decoders. The complete system has been simulated and tested in SystemC Platform.