Robustness oriented design tool for multilayer DTCNN applications
Paula Lopez, D.L. Vilariño, V.M. Brea, D. Cabello · International Journal of Circuit Theory and Applications · 2002
Abstract In this work, we present a design automation tool for the synthesis of multilayer discrete time cellular neural network (DTCNN) structures that takes into account hardware implementation constraints. In so doing, the possible implementation on a VLSI CNN chip of the solutions found is guaranteed. The algorithm is based on stochastic optimization strategies, particularly genetic algorithms. In order to guarantee correct operation of analog VLSI chips the robustness of the templates and the network complexity have been considered during the optimization process by means of the introduction of penalty functions. This strategy has the side effect of reducing the computational cost of the optimization process since it focuses on those areas of the search space that meet the implementation requirements. As a difference from previous approaches to robust template design, the problem of robustness in greyscale input applications is also considered under the assumption of an appropriate selection of the training set, that must not only define the task but also contain relevant information about the images to be processed. Copyright © 2002 John Wiley & Sons, Ltd.