A Verifying Method of Controller Synthesis
Wei Li, Ying Lu, Yichao Zhang, Jian-Guo Wu · 2008
Verifying of controller synthesis’ correctness is studied in this paper, which is based on completely specified finite state machine. We obtain some useful information by verifying two graphs‘ isomorphism, which is about the corresponding controller synthesis’ correctness. First get behavior description by inverse analyzing, then design a verifying method based on STG’s (State Transition Graph) isomorphism, finally analyzing the time complexity.