VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight
Yang Sun, Joseph R. Cavallaro · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2012
In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K ≥ 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z×Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm2, the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations.