Optimizing software performance for IP frame reassembly in an integrated architecture
Peter M. Ewert, Naraig Manjikian · 2000
This paper investigates the control software performance for IP frame reassembly on an integrated single-chip architecture in order to identify effective techniques for optimizing the performance of embedded software for similar applications.The architecture combines a single processor, memory, and embedded direct-memory-access (DMA) engines to allow for the reception of ATM cells, and reassembly and transmission of IP frames.The paper introduces the base software design that was implemented to orchestrate the DMA engines and manage the reassembly of the ATM cells.In order to improve the control software performance, a number of optimizations are described, such as blocking, prefetching, and merging.The performance of both the base and optimized versions of the software is investigated with detailed event-driven timing simulation, including the effect of caching and contention for the bus and memory.Simulation results indicate that the base software can support OC-12 rates with a 500MHz processor when a small segment of memory is used for ATM cell buffering.The optimized version of the software reduces the minimum processor speed to 300Mhz.