Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
Jiangyi Shi, Mingxing Wang, Yinghui Tian, Zhe Yang · 2012
CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods are given in this paper. Then, the hardware pipelining structure of the CORDIC multiplier is put forward. Comparison results about RTL simulation results with MATLAB calculation indicate that the design is feasible and practical.