Automated technique for high-level circuit synthesis from temporal logic specifications
R.D. Dowsing, R. Elliott, I. Howard Marshall · IEE Proceedings - Computers and Digital Techniques · 1994
A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined.