An abstract parallel graph reduction machine
Kenneth R. Traub · ACM SIGARCH Computer Architecture News · 1985
An implementation technique for functional languages that has rcceived recent attention is graph reduction, which offers opportuniqt for the exploitation of parallelism by multiple processors.While several proposals for parallel graph reduction machines have been made, differing terminology and approaches make these proposals dimcuk to compare.This paper presents a systematic approach to the study of parallel graph reduction machines, and proposes an abstract architecture for such a machine that is independent of the base language and communication network chosen for an actual implementation.The abstract architecture, in addition to serving as a foundation for the design of real machines, highlights the necessary features of all parallel graph reduction machines.