Development of Fixed-point Simulataneous Square Root and Logarithm Operations for High-level Synthesis
Kazunari Yoshikawa, Naohiro Iwanaga, Tatuya Hamachi, Akira Yamawaki · 2014
When developing a hardware module performing some signal processing, we first design the algorithm in high level language like C. Next, we describe the behavior of the hardware module in hardware description language (HDL), referring to the C program previously written. Finally, a synthesis tool generates the real hardware from the HLD program. High-level synthesis technology (HLS) is a technology automatically converting C programs into the HDL programs. HLS can reduce the designing load of the hardware module by skipping the development of the HLD program. We are developing a fixed-point generic HLS library of elementary functions that is able to be converted by HLS. This paper focuses on simultaneous square root and logarithm operation in elementary functions. This paper shows that designing a fixed-point program in C language of simultaneous square root and logarithm operation by the coordinate rotation digital computer, CORDIC algorithm. To evaluate the hardware size and the operational speed of our operation, we convert it to the HDL program for an FPGA by Xilinx Vivado HLS tool. The experiment compares our hardware generated with the conventional floating point hardware generated from the math library. Although the conventional one is converted to the netlist dedicated to the specified device, the results show that our programs can decrease hardware size than the conventional one and achieve the equivalent performance. Our hardware library for HLS is the device-independent while the conventional one is converted to the netlist highly dependent on the specified device. Thus, our library have higher versatility than the conventional one.