A composite CMOS gate array with 4K RAM and 128K ROM
N. Miyahara, K. Ishikawa, Shigetatsu Hamaguchi, S. Horiguchi, Masanao Aoki · IEEE Journal of Solid-State Circuits · 1986
A unique gate array structure, called a composite gate array, incorporating a RAM and a ROM along with ordinary gate arrays, is described. The composite gate array consists of a 128K ROM, a 4K RAM, and a 6K gate array, and is developed using 1.6-/spl mu/m CMOS technology. The RAM and ROM are partitioned into four 1K and eight 16K blocks for increasing flexibility of memory configuration. A distributed arrangement of memory blocks is used to permit completely automatic writing using fewer channels. In circuit performance, gate delay time is 1.0 ns, RAM access time is 25 ns, and ROM access time is 30 ns. A communication control processor for personal computer networks is successfully designed to demonstrate the feasibility of the gate array.