An Efficient Finite Field Multiplier Using Redundant Representation
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi · ACM Transactions on Embedded Computing Systems · 2012
An efficient word-level finite field multiplier using redundant representation is proposed. The proposed multiplier has a significantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC’s .18 um CMOS technology for the binary field size of 163 is also presented.