Runtime power reduction capability of the IBM POWER7+ chip
M. S. Floyd, Alan J. Drake, Nicole Schwartz, R. W. Berry, Charles R. Lefurgy, M. Ware, Karthick Rajamani, Victor V. Zyuban, Richard L. Willaman, R. M. Zgabay · IBM Journal of Research and Development · 2013
Four new energy management features in the POWER7+™ chip enable larger reductions in chip power consumption and further increase energy efficiency of the system during runtime compared with prior POWER7® systems. First, per-core power gating reduces idle power consumption by allowing the system to turn off the voltage to the processor cores when they are not being used. Second, real-time measurement and control of operational guardband allows for higher maximum clock frequency as well as better dynamic voltage selection to reduce power. Third, per-thread utilization counters enable the firmware to sense processor utilization on a finer granularity and set per-core frequency targets with greater accuracy. Finally, a per-core memory access counter allows firmware to more accurately account for power consumption and budget it on a per-processor core basis. These hardware capabilities together enable new EnergyScale™ firmware functions that include voltage optimization to achieve higher turbo frequencies under stressful environmental conditions, automated idle state detection and management, per-core adaptive frequency scaling, and online power modeling for real-time estimation of energy savings.