Hardware Architecture Optimized for Iris Recognition
Kamil Grabowski, Andrzej Napieralski · IEEE Transactions on Circuits and Systems for Video Technology · 2011
One of the remaining problems in iris recognition is the implementation of its efficient hardware systems. The difficulty arises from the fact that the methods forming part of this type of authentication process are fairly complex. Furthermore, next generation algorithms for iris recognition will become even more complex to enhance the reliability and functionality of currently used solutions. An example of such an intensive processing task is iris image quality assessment and segmentation using video signal obtained at-a-distance and on-the-move. Thus, processing robustness and predictable analysis time in such dedicated architectures may be particularly important. This paper describes a hardware system designed to analyze iris biometric data developed as a part of the work conducted by the authors on the complete iris identification system (1:N). This specialized architecture is mainly composed of digital signal processors and field-programmable gate arrays. Several issues concerning efficient biometric sample processing are discussed. Algorithms for iris recognition previously developed by the authors on a PC platform were adapted to the described architecture. The obtained results are presented, and the developed system is compared with chosen commercially available iris authentication systems.