Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation
Shen‐Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher · IEEE Transactions on Circuits & Systems II Express Briefs · 2014
Table-lookup-and-addition methods provide multiplierless function evaluation using multiple lookup tables and a multioperand adder. In spite of their high-speed operation, they are only practical in low-precision applications due to the fast increase in table size with precision width. In this brief, we present two methods for table size reduction by decomposing the original table of initial values into two or three tables with fewer entries and/or smaller bit width. The proposed table decompositions do not incur any extra rounding errors so that the original table can be completely recovered. Experimental results demonstrate significant saving of table sizes compared with the best of the prior designs of the multipartite methods.