Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors
Navneet Basutkar, Ho Yang, Peng Xue, Kitaek Bae, Young-Hwan Park · 2013
This paper describes the feasibility of software implementation of DVB-T2 receiver with DTG-106 [1] mode using the coarse-grained reconfigurable array (CGRA) based processor. This paper focuses mainly on DVB-T2 system design and implementation of major software functions of DVB-T2 demodulator: FFT, frequency interpolation, multi-level de-interleaving, and soft-demapper. By implementing the full chain DVB-T2 software and measuring the cycle performance, we demonstrate the software implantation of DVB-T2 on dual core CGRA processor running at 400MHz.