A Novel ATPG Method for Capture Power Reduction during Scan Testing
Xianshan Wen, Seiji Kajihara, Kohei Miyase, T. Suzuki, Kewal K. Saluja, L.-T. Wang, Keisuke Kinoshita · IEICE Transactions on Information and Systems · 2007
High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era.This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction.Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation.Experimental results show its effectiveness.