The ERSO 1.2 mu m standard cell design system
W.Y. Chang, R.H. Fong, C.C. Lou, H.C. Lee, Y.A. Liang, J.C. Hsieh, L.C. Chang, Pengfei Huang, R.C. Lee · International Symposium on VLSI Technology, Systems, and Applications · 2003
A 1.2- mu m standard-cell design system has been designed for system-level integration. It contains 200 primitive SSI (small-scale integration) cells, 53 soft-coded MSI (medium-scale integration) cells, and compilable RAM (random-access memory), ROM (ready-only memory), and PLA (programmable logic array). Four chips-a 12500-gate-count enhanced video graphic array (EVGA), a SSI, and MSI, and a compilable cell test chip-have been designed to verify the design system.>