18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS
Rajaraman Ramanarayanan, Sanu K. Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A Anders, Vasantha Erraguntla, Ram Kumar Krishnamurthy · 2010
A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm2with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <;3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range.