Fault resilience of the algebraic multi-grid solver
Marc Casas, Bronis R. de Supinski, Greg Bronevetsky, Martin Schulz · 2012
As HPC system sizes grow to millions of cores and chip feature sizes continue to decrease, HPC applications become increasingly exposed to transient hardware faults. These faults can cause aborts and performance degradation. Most importantly, they can corrupt results. Thus, we must evaluate the fault vulnerability of key HPC algorithms to develop cost-effective techniques to improve application resilience.