Linear interconnection architecture in parallel implementation of neural network models
M. Taghi Mostafavi · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1991
An architecture for VLSI/ULSI implementation of neural network models is presented. The architecture is of the linear and systolic type and can easily be expanded to a larger network size with more processing elements per layer and/or more layers per network model. The weights in this architecture are fully adjustable. The weights must be pre-computed with the help of a host computer and downloaded to the system as a preinitialized process. This architecture is basically suitable for feed forward neural network architecture. 1.