Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns
Ioannis Voyiatzis · 2014
In this work we present a new scheme for the on-chip application of test patterns utilizing an accumulator structure whose inputs are driven by a barrel shifter. The consecutive patterns applied to the inputs of the Circuit Under Test differ in one bit, therefore the power consumed is lower compared to previously proposed accumulator-based pattern application schemes.