Power efficient partial product compression
Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen · 2011
We present a power efficient structure for partial product compression. Since the full-adder cell is a cornerstone for partial product compression, we determined what are the most power efficient full-adder cells for a wide range of delays. We then developed a new delay-based partial product wiring algorithm that uses the faster XOR-based full adder when one input is a gate delay slower in arriving and otherwise uses the more area efficient mirror-based full adder. We show that this new wiring algorithm is more power efficient than the use of only one type of full adder. Compared to the leading automatic synthesis tool, our approach yields better power efficiencies (lower active area for the same delay) as well as lower delays. For the summation of 16 16-bit vectors, our approach reduces active area by 45% for the same delays produced by the leading synthesis tool.