FPGA architectures as device-flexible macros
Kengo R. Azegami, Koichi Yamashita · Electronics and Communications in Japan (Part II Electronics) · 1998
An FPGA (field programmable gate array) architecture that can be realized as a macro on any type of device is described. Various products use FPGAs among their components; however, they use them in combination with other LSIs (such as custom designed LSIs). The aim of our macro-type FPGA architecture is to provide the means for creating programmable regions of any size and shape, on any type of device, and finally, to combine the traditional multi-LSI systems into one chip. To make our architecture device independent, inside the logic cells, we simplified the structure of the logic component and separated it from the program memory. Since the logic cells are designed as minimum units of the macro, programmable regions of any size and shape can be easily achieved by placing the desired number of logic cells in the desired configuration. The details of our architecture were determined through experiments. As a sample realization, we implemented our architecture on a three metal layer CMOS SOG (sea of gates) gate array. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(5): 51–58, 1998