An Architecture for Bitonic Sorting with Optimal VLSI Performnance
Gianfranco Bilardi, Franco P. Preparata · IEEE Transactions on Computers · 1984
We propose a class of designs of a new interconnection network, the pleated cube-connected cycles (PCCC), which can impleement stable bitonic sorting of n records of size q in area A = O(q2n2/T2), where T, the computation time, is in the range [Ω(q log2n), O(q √n/(q+ log n))]. Thus, this network is an AT2,/R-optimal bitonic sorter in the synchronous VLSI model of computation under the word-local restriction.