A high-speed low-cost DCT architecture for HDTV applications
Z.-J. Mou, F. Jutand · 1991
An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware.>