Revisiting shared virtual memory systems for non-coherent memory-coupled cores
Stefan Lankes, Pablo Reble, Oliver Sinnen, Carsten Clauß · 2012
The growing number of cores per chip implies an increasing chip complexity, especially with respect to hardware-implemented cache coherence protocols. An attractive alternative for future many-core systems is to waive the hardware-based cache coherency and to introduce a software-oriented approach instead: a so-called Cluster-on-Chip architecture. The Single-chip Cloud Computer (SCC) is a recent research processor of such architectures.