Concurrent error detection and fault location in an FFT architecture
Fabrizio Aghini Lombardi, Jon C. Muzio · IEEE Journal of Solid-State Circuits · 1992
A new approach for concurrent error detection in a homogeneous architecture for the computation of the complex N-point fast Fourier transform (FFT) in radix-2 is presented. The proposed approach is based on the relationship between cell computations. It is proved that 100% probability of detection is possible. Overhead issues for hardware and timing are addressed. It is proved that hardware overhead for concurrent error detection is 50% compared to a fault-intolerant complex two-point implementation. A modest time overhead is encountered for error detection and fault location. Error detection can be accommodated online and on a component basis (multiplier or adder/subtractor): full fault location is accomplished by a roving technique. The proposed technique can be efficiently accommodated in a homogeneous layout. A two-phase reconfiguration policy for the proposed architecture is presented. It is proved that switching and routing overhead is modest, while reliability is significantly improved over previous approaches.>